The invention relates to a testable on-chip capacitor cell including a decoupling capacitor which is connected to the chip power supply system for serving a high frequency current demand during highly synchronous on-chip switching activity. The invention also relates to an integrated semiconductor chip containing a plurality of testable decoupling capacitors and to a method for testing on-chip decoupling capacitors.
On-chip power supply decoupling capacitors are used to stabilize the on-chip power supply system of synchronously clocked CMOS chips. The highly synchronous on-chip switching activity and its associated high frequency current demand prevents to rely only on off-chip power supply decoupling capacitors. The inductive connection paths between on-chip switching circuitry and off-chip power supply decoupling capacitors do not allow to transfer high amounts of charge in a short time. The initial charge demand of an on-chip switching event has to be served first from on-chip power supply decoupling capacitors. Recharging of the on-chip decoupling capacitors from off-chip capacities happens afterwards with lower speed.
WO96/33495 discloses on-chip power supply decoupling capacitors which are directly connected to the on-chip power distribution network. The capacitors may be implemented by CMOS devices. The known circuit includes self-repairing capabilities by using a cross-coupled structure which reacts to a leakage current in one of the transistors to switch into another state. Such circuit facilitates the testability of the whole chip by reducing keeping leakage currents initiated by coupling capacitors. The circuit does not deal with the testability of on-chip power supply decoupling capacitors and the measurement of their actual capacity values.
It is an object of the invention to propose an on-chip power supply decoupling capacitor cell which is testable and which permits to measure its capacity value.
It is also an object of the invention to provide an integrated semiconductor chip including a plurality of testable and measurable on-chip power supply decoupling capacitors distributed over the chip area.
It is a further object of the invention to provide a method for testing and measuring on-chip power supply decoupling capacitors which are connected to a power supply distribution network.
According to the invention, as defined in the claims, an on-chip power supply decoupling capacitor cell is proposed which can be disconnected from the power distribution network and discharged through a cell internal discharge circuit. An externally controllable switch connects in a first switching position the decoupling capacitor to the power supply system and disconnects in a second switching position the decoupling capacitor from the power supply system and connects it instead to a resistor which is part of the discharge circuit. Control means are provided externally of the chip for toggling the switch with a frequency between its first and second position to perform a capacitor test operation. Furthermore, means are provided for measuring the power supply current of the decoupling capacitor when said switch is toggled and for determining the actual capacity of the decoupling capacitor.
The cell allows to test the on-chip power supply capacitor and to determine its capacity value by measuring the power supply current IPS during toggling of the control input of a switch which alternately connects the on-chip power supply capacitor to the power distribution network and the discharge resistor. The capacity value can be calculated from the measured power supply current IPS, the power supply voltage UPS and the switch toggling frequency fT.
Another aspect of the invention is to provide a semiconductor chip which contains a plurality of on-chip power supply decoupling capacitor cells according to the invention.
Furthermore, according to the invention a method is provided for testing and measuring on-chip power supply decoupling capacitors. The method comprises the step of toggling with a frequency fT a plurality of externally controllable on-chip switches each of which being assigned to one of a plurality of power supply decoupling capacitors to connect in a first switch position a first capacitor terminal to a power supply distribution network and to connect in a second switch position the first capacitor terminal through a discharge resistor to a line of the power supply distribution network to which line also a second capacitor terminal is connected. The method further comprises the steps of measuring the power supply current IPS of the power supply decoupling capacitors and of determining the actual capacity of the decoupling capacitors from the voltage applied to the power supply lines, the switch toggling frequency fT and the supply current measured.
The invention allows testability of power supply decoupling capacitors during manufacturing on wafer and/or module level which results in an improved product quality level. It also allows a capacity design verification in the presence of capacitive influences of a parasitic environment. Furthermore, the invention permits to assure defect free decoupling capacitors during the power-on phase and a verification of proper power supply stability in case of intermittent fails. The invention also provides an enhancement of the selftest capabilities and of reliability tests.